CAD for VLSI

A distributed EDA framework for scalable design management

Internship: IBN System Development Labs India In a typical design flow, multiple tools and scripts are used. Each tool reads the input, its associated constraints, processes and generates data as output. At present there is no mechanism to represent this data in a database which limits the possibility of live query on the data and get a useful information and value add out of it. For example: to find a timing critical path it requires to load a timer which in turn processes the input and eventually writes out report.

AI-guided heurisitics for Leakage Power Minimzation in Digital Circuits

Power optimization techniques in a VLSI flow typically end up being the performance bottlenecks leading to a large turn around time for the following reasons 1. Scalability: The design typically spans millions and millions of gates with different operating conditions leading to a large search space. 2. Portability: The constraints vary across technology nodes hindering reusability of solutions. ML models are inherently trained to operate on large datasets and navigate a complex search space.

RTL-level Security estimation of digital designs

Embedded devices have started playing an increasing role in our day-to-day lives, due to the emergence of IoT, leading to the question ”Can these devices be trusted?”. The emergence of side-channel attacks in the recent years has shown that the underlying hardware too has to be secured. This quest for quantifying the resilience of the device to the side channels has led researchers to develop several statistical metrics. However, these metrics i) quantify the security of a manufactured device, thereby functioning only in a preventive capacity ii) they do not explore or identify the root cause of the vulnerability.