Journal

TREEHOUSE: A Secure Asset Management Infrastructure For Protecting 3DIC Designs

The push to meet growing user requirements and manufacturing challenges at lower technology nodes have motivated chip designers to adopt non-traditional design techniques. 2.5D/3DIC stacking has gained popularity in recent years since it enables chip …

SIGNED: A Challenge-Response Scheme for Electronic Hardware Watermarking

Hardware Watermarking is one of the popular countermeasures to prevent hardware counterfeiting. A robust watermark has to be invisible to the attacker, yet allow the verifier to access it easily. It should also be resistant to design transformations …

RIHANN: Remote IoT Hardware Authentication With Intrinsic Identifiers

The heterogeneous array of edge devices in an Internet of Things (IoT) infrastructure is increasingly vulnerable to physical in-field tampering attacks. These devices can significantly benefit from a difficult-to-clone and tamper-immune intrinsic …

On Database-Free Authentication of Microelectronic Components

Counterfeit integrated circuits (ICs) have become a significant security concern in the semiconductor industry as a result of the increasingly complex and distributed nature of the supply chain. These counterfeit chips may result in performance …

Trust Issues in Microelectronics: The concerns and the countermeasures

The semiconductor industry is constantly striving to improve the performance, reliability, and cost of electronic devices. The growing complexity in the design process of microelectronics coupled with the requirement of significant investment in …

Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER

Cache timing attacks are a serious threat to the security of computing systems. It permits sensitive information, such as cryptographic keys, to leak across virtual machines and even to remote servers. Encrypted Address Cache, proposed by CEASER - a …

MLTimer: Leakage Power Minimisation in Digital Circuits using Machine Learning and Adaptive Lazy Timing Analysis

The timing constrained discrete sizing technique (TC-DSP) is employed at all stages of the physical synthesis flow and has been studied extensively over the last 30 years. The ISPD gate sizing contests introduced industry standard benchmarks and …

GANDALF: A fine-grained hardware-software co-design for preventing memory attacks.

Illegal memory accesses are a serious security vulnerability that have been exploited on numerous occasions. In this letter, we present Gandalf, a compiler assisted hardware extension for the OpenRISC processor that thwarts all forms of memory-based …