Embedded devices have started playing an increasing role in our day-to-day lives, due to the emergence of IoT, leading to the question ”Can these devices be trusted?”. The emergence of side-channel attacks in the recent years has shown that the underlying hardware too has to be secured. This quest for quantifying the resilience of the device to the side channels has led researchers to develop several statistical metrics. However, these metrics i) quantify the security of a manufactured device, thereby functioning only in a preventive capacity ii) they do not explore or identify the root cause of the vulnerability. Critical Outcomes: 1. Identifying the optimizations/changes made to the device during the transition from a High level language (eg: Verilog) to actual hardware and quantifying its impact to the security of the device. 2. Propose a security aware power optimization scheme that takes in to account the security metric along with the other design constraints (KARNA ICCAD’19’). 3. Developed an RTL-level framework that would help designers map the vulnerable RTL-code to their corresponding gate-level or layout-level counterpart (SOLOMON DATE’2018). 4. Developed a gate-sizing framework for optimization gates to meet both security and power objectives (AVATAR ASPDAC’2022).
