Hardware Security

Trust Issues in Microelectronics: The concerns and the countermeasures

The semiconductor industry is constantly striving to improve the performance, reliability, and cost of electronic devices. The growing complexity in the design process of microelectronics coupled with the requirement of significant investment in …

Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER

Cache timing attacks are a serious threat to the security of computing systems. It permits sensitive information, such as cryptographic keys, to leak across virtual machines and even to remote servers. Encrypted Address Cache, proposed by CEASER - a …

Srivastava 2020 Solomon

Fault attacks are potent physical attacks on crypto-devices. A single fault injected during encryption can reveal the cipher's secret key. In a hardware realization of an encryption algorithm, only a tiny fraction of the gates is exploitable by such …

Karna: A gate-sizing based security aware eda flow for improved power side-channel attack protection

Power side-channel attacks pose a serious threat to the security of embedded devices. Most available countermeasures have significant overheads resulting in the application not meeting its requirements of low-power, high-performance and small area. …

GANDALF: A fine-grained hardware-software co-design for preventing memory attacks.

Illegal memory accesses are a serious security vulnerability that have been exploited on numerous occasions. In this letter, we present Gandalf, a compiler assisted hardware extension for the OpenRISC processor that thwarts all forms of memory-based …

Automatic Implementation of Secure Silicon

The primary goal of the DARPA AISS project is to develop secure System on Chips (SoCs) that can be widely used by designers with varying range of security expertise. However, it is also crucial to ensure that the security architectures are compliant with the power, performance, and area requirements. Critical Outcomes produced 1. Developed and demonstrated a proof-of-concept implementation a complete SoC implementation with hardware and firmware support for integrating PUF, Logic Locking protocols, and IP watermarking techniques.

Lightweight Authentication Protocols for securing IoT Devices

Counterfeit integrated circuits (ICs) have become a significant security concern in the semiconductor industry as a result of the increasingly complex and distributed nature of the supply chain. These counterfeit chips may result in performance degradation, profit reduction, and reputation risk for the manufacturer. Therefore, developing effective countermeasures against such malpractices is becoming severely crucial. As a part of our research effort we develop lightweight authentication techniques using Physically Unclonable Functions (PUFs) and watermarks for detecting counterfeit ICs.

RTL-level Security estimation of digital designs

Embedded devices have started playing an increasing role in our day-to-day lives, due to the emergence of IoT, leading to the question ”Can these devices be trusted?”. The emergence of side-channel attacks in the recent years has shown that the underlying hardware too has to be secured. This quest for quantifying the resilience of the device to the side channels has led researchers to develop several statistical metrics. However, these metrics i) quantify the security of a manufactured device, thereby functioning only in a preventive capacity ii) they do not explore or identify the root cause of the vulnerability.